module source_pb(
    input               clk                     ,
    input               rstn                    ,
    input       [7:0]   data_i ,
    output  reg [7:0]  data_o,
    //slave signal
    input           valid_i,
    output          ready_o,
    //master signal
    input           ready_i,
    output              valid_o
);
reg [7:0] temp_a,temp_b;
reg  valid_r1,valid_r2,valid_r3;
wire ready_r1,ready_r2;

//  valid_r1为0代表下一级无数据
//    ready_r1代表下一级准备好了读
assign ready_o = ~valid_r1 || ready_r1; //pre-fetch结构   

//pipeline stage 1
always @(posedge clk) begin 
    if(!rstn)begin
        valid_r1    <= 1'b0;
    end
    else if(ready_o)begin           //如果本级准备好了，则将上一级的valid信号传递下来
        valid_r1    <= valid_i;
    end
end
always @(posedge clk or negedge rstn)begin              
    if(!rstn)begin
        valid_r1 <= 1'b0;
    end
    else if(ready_o & valid_i)begin  //输入数据ready-valid信号同时拉高时，数据有效并传入。
        temp_a <= data_i;
    end
end
//pipeline stage 2
assign ready_r1 = ~valid_r2 || ready_r2;
always @(posedge clk) begin 
    if(!rstn)begin
        valid_r2    <= 1'b0;
    end
    else if(ready_r1)begin           //如果本级准备好了，则将上一级的valid信号传递下来
        valid_r2    <= valid_r1;
    end
end
always @(posedge clk or negedge rstn)begin                                      
    if(!rstn)begin
    end
    else if(ready_r1 & valid_r1)begin
           temp_b <= temp_a;
    end
end                                                                                            
//pipeline stage 3
assign ready_r2 = ~valid_r3 || ready_i;
always @(posedge clk) begin 
    if(!rstn)begin
        valid_r3    <= 1'b0;
    end
    else if(ready_r2)begin           //如果本级准备好了，则将上一级的valid信号传递下来
        valid_r3    <= valid_r2;
    end
end
always @(posedge clk or negedge rstn)begin
    if(!rstn)begin
    end
    else if(ready_r2 & valid_r2)begin
        data_o <= temp_b;
    end
end
assign valid_o = valid_r3;
endmodule
                                                                                                                
                                                                                                    
